1. Field of the Invention
The present invention relates to electronics, and, in particular, to phase-locked loops.
2. Description of the Related Art
A phase-locked loop (PLL) is a circuit that generates a periodic output signal that has a constant phase relationship with respect to a periodic input signal. PLLs are widely used in many types of measurement, microprocessor, and communication applications. One type of phase-locked loop is the charge-pump: PLL, which is described in Floyd M. Gardner, xe2x80x9cCharge-Pump Phase-Lock Loopsxe2x80x9d IEEE Trans. Commun., vol. COM-28, pp. 1849-1858, November 1980, the teachings of which are incorporated herein by reference.
FIG. 1 shows a block diagram of a conventional charge-pump phase-locked loop 100. Phase detector (PD) 102 compares the phase xcex8IN of the input signal FIN to the phase xcex8OUT of the feedback signal FOUT and generates an error signal: either an UP signal U(when xcex8IN leads xcex8OUT) or a DOWN signal D (when xcex8OUT leads xcex8IN), where the width of the error signal pulse indicates the magnitude of the difference between xcex8IN and xcex8OUT.
Charge pump 104 generates an amount of charge equivalent to the error signal (either U or D) from PD 102. Depending on whether the error signal was an UP signal or a DOWN signal, the charge is either added to or subtracted from the capacitors in loop filter 106. For purposes of this explanation, loop filter 106 has a relatively simple design, consisting of a capacitor CS in parallel with the series combination of a resistor R and a relatively large capacitor CL. As such, loop filter 106 operates as an integrator that accumulates the net charge from charge pump 104. Other, more-sophisticated loop filters are of course also possible. The resulting loop-filter voltage VLF is applied to voltage-controlled oscillator (VCO) 108. A voltage-controlled oscillator is a device that generates a periodic output signal (FOUT in FIG. 1), whose frequency is a function of the VCO input voltage (VLF in FIG. 1). In addition to being the output signal from PLL 100, the VCO output signal FOUT is used as the feedback signal for the closed-loop PLL circuit.
Optional input and feedback dividers 110 and 112 may be are placed in the input and feedback paths, respectively, if the frequency of the output signal FOUT is to be either a fraction or a multiple of the frequency of the input signal FIN. If not, the input and feedback dividers can both be considered to apply factors of 1 to the input and feedback signals, respectively.
Charge-pump PLL 100 of FIG. 1 is an example of an analog PLL, in which VCO 108 is controlled by an analog input signal VLF generated by charge pump 104 and loop filter 106. Digital phase-locked loops are also known.
FIG. 2 shows a block diagram of a conventional digital phase-locked loop 200. PLL 200 is similar to PLF 100 of FIG. 1, except that charge pump 104 and loop filter 106 are replaced by a digital accumulator and filter 204 and voltage-controlled oscillator 108 is replaced by a digitally controlled oscillator (DCO) 208, which receives an externally generated, high-speed clock signal having frequency FHSCK.
In operation, input divider 210, phase detector 202, and feedback divider 212 of PLL 200 operate analogously to input divider 110, phase detector 102, and feedback divider 112 of PLL 100, respectively. Instead of generating an analog voltage control signal, digital accumulator and filter 204 accumulates and filters the UP and DOWN signals generated by PD 202 to generate a digital control signal M, which has a positive integer value. DCO 208 uses the digital control signal M to convert the high-speed clock signal FHSCK into the PLL output signal FOUT according to Equation (1) as follows:
FOUT=FHSCK/M.xe2x80x83xe2x80x83(1)
Since Equation (1) represents a division operation, in a conventional digital PLL, DCO 208 is implemented as a simple digital divider.
One application for PLLs is in frequency synthesizers with high multiplication ratios. For example, it may be desirable to implement a PLL having a multiplication ratio as high as 77,750 in order to convert an input signal FIN having a frequency of 8 kHz into a phase-locked output signal FOUT having a frequency of 622 MHz. In order for the feedback loop of a charge-pump PLL to remain stable, the frequency of the inputs to the phase detector must exceed the PLL closed-loop bandwidth. A typical ratio is 10. This means that, in order to use a charge-pump PLL for the previous example of a high-multiplication frequency synthesizer, the PLL closed-loop bandwidth should be on the order of 0.8 Hz.
Another application for PLLs is in clock filtering. Some clock filtering applications, such as SONET clock filtering, require PLL closed-loop bandwidths as low as 0.1 Hz.
One problem with using charge-pump PLLs in applications such as high-multiplication frequency synthesizers and clock filtering that have low closed-loop bandwidths, relates to noise. Charge-pump PLLs do not provide a large amount of cancellation of intrinsic noise generated within the feedback loop. As a result, for low-noise applications, PLL closed-loop bandwidth is usually maximized.
In light of these competing goals, charge-pump PLLs are often not suitable for applications requiring both a high degree of stability and a low amount of noise.
In general, it would be desirable to implement PLLs for applications such as high-multiplication frequency synthesizers and clock filtering, as part of digital ASICs (application-specific integrated circuits). One known way to integrate analog PLLs into digital ASICs is to base the VCO on a ring oscillator. A ring oscillator is a set of delay cells connected head to tail, whose output frequency is controlled by a voltage control signal applied to all of the delay cells. As mentioned before, in order to have low noise, a charge-pump PLL must have a relatively high loop bandwidth in order to allow the PLL feedback loop to cancel (or at least significantly reduce) internally generated noise. This in turn requires that the frequency at the phase detector (i.e., the PD update rate) also be large in order for the PLL to remain stable. However, since PLL applications, such as high-multiplication frequency synthesizers and clock filtering, require relatively low PLL loop bandwidths and the large multiplication value implies a relatively low input frequency for a fixed output frequency, it is impractical to integrate conventional ring-oscillator-based analog PLLs, such as charge-pump PLL 100 of FIG. 1, into digital ASICs for such applications.
It is also impractical to use conventional digital PLLs, such as PLL 200 of FIG. 2, in applications such as high-multiplication frequency synthesizers. Because the digitally controlled oscillator 208 simply divides down the input clock signal FHSCK, in order to accurately generate a PLL output signal FOUT having a frequency as high as 622 MHz, FHSCK must have a frequency much higher than 622 MHz. This may be impractical in many applications. This is even more true for applications that require PLL output signals having frequencies greater than 622 MHz (e.g., as high as 1 GHz or even higher).
The present invention is directed to a PLL design that addresses limitations in the prior art. In particular, PLLs of the present invention can be used in applications such as high-multiplication frequency synthesizers and low-bandwidth clock filtering that are integrated into digital ASICs without having to sacrifice low-noise performance.
In one embodiment, the present invention is an integrated circuit (IC) having a phase-locked loop (PLL), the PLL comprising (a) a phase detector (PD), configured to receive a PLL input signal and a PLL feedback signal and to generate PLL PD signals based on differences in phase between the PLL input and PLL feedback signals; (b) an accumulator/filter, configured to receive the PLL PD signals from the phase detector and to generate a digital control signal; and (c) a digitally controlled oscillator (DCO), configured to:
(1) receive (i) the digital control signal from the accumulator/filter and (ii) an oscillator clock signal; and
(2) to generate an output signal whose frequency is (i) based on the digital control signal and (ii) greater than the frequency of the oscillator clock signal, wherein the PLL feedback signal is generated from the output signal.